In many advanced computer system components, powerful debug mechanisms are implemented to detect various internal debug related events, to select appropriate ones for analysis by other on-chip mechanisms, and to use results to trigger internal responses. These response mechanisms, such as forcing various error and throttling conditions, forcing freezing/breaking, and others, are critical to a variety of debug purposes.
It is often advantageous to pass debug information between components in a computer system. Prior computer systems have used a limited number of dedicated signal lines to pass debug information between computer system components. In these prior systems, each of the components participating in the sharing of debug information must dedicate one or more signal pins to passing debug information. The limited number of signal lines restricts the amount of debug information that can be passed between components. The dedicated signal pins result in increased component packaging costs.